1. Field of the Invention
This invention relates to integrated circuit fabrication and more particularly to a high density metallization technique employing an interconnect formed laterally adjacent a patterned structure, wherein the resulting interconnect has a vertical sidewall surface.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon to form an integrated circuit. The entire process of making an ohmic contact to the contact areas and routing interconnect material between ohmic contacts is described generally as "metallization". While materials other than metals are often used, the term metallization is generic in its application. It is derived from the origins of interconnect technology, where metals were the first conductors used. As the complexity of integrated circuits has increased, the complexity of the metallization structure has also increased.
In general, the formation of interconnect routing between ohmic contacts first involves depositing a conductive material across the surface of a semiconductor topography embodying ohmic contact areas. Interconnects may need to extend relatively long distances across an integrated circuit to reach contacts. Therefore, it is popular to use a conductive material which exhibits low resistivity, such as aluminum or aluminum alloy. A photolithographic pattern consisting partially of stripes is formed upon the conductive material. An optical image and a photosensitive film are used to produce the interconnect pattern. The photosensitive film (i.e., photoresist) has two main properties: when exposed to appropriate radiation, resist solubility is altered, allowing certain areas to be easily washed away by a solvent; and when exposed to an etchant capable of removing the conductive material, it resists attack. Thus, to complete the formation of interconnect, areas of the conductive material not covered by photoresist are etched away using an etchant that exclusively attacks those areas.
A problem with the above-mentioned method for the formation of interconnect is that etching results in interconnects having sloped sidewall surfaces. Sloped sidewall surfaces particularly result when using isotropic etching which occurs laterally and obliquely at a relatively uniform rate in all directions. Thus, anisotropic etching has become popular in integrated circuit manufacturing because it allows the downward etch rate to be much larger than the lateral etch rate, resulting in less sloping of interconnect sidewall surfaces. However, even with the advent of anisotropic etch technology, sidewall surfaces of interconnect still exhibit an undesired amount of sloping (i.e., is not substantially vertical to the underlying topography surface).
Turning to FIG. 1a, a cross-sectional view of interconnect 10 is shown patterned upon a relatively planar topography 14. Patterned interconnect 10 results from conventional etchant as having such a sloped sidewall surface 16. A patterned photoresist layer 12 is shown lying directly above interconnect 10 being formed. Unfortunately, during etching, the top portion of interconnect 10 under photoresist layer 12 is oftentimes removed somewhat. Removal at the upper portion occurs at a faster rate than the bottom portion, most likely due to the isotropic component of conventional etchants. The result of such etching is that the base of interconnect 10 is be wider than its upper surface. This result is sometimes referred to as "undercutting". A detailed view of sidewall surface 16 is illustrated in FIG. 1b. The resulting sidewall surface 16 is shown non-perpendicular to the horizontal topography 14 upon which interconnect line 10 is disposed. Therefore, an angle 20 between sidewall surface 16 and surface 14 is less than ninety degrees. Dashed line 18 represents an ideal sidewall surface as being vertical.
Current density is dependent on the actual cross-sectional area of an interconnect line. The cross-sectional area of an interconnect must be large enough to accommodate a pre-determined current density. Thus, since conventional interconnect are wider at the bottom than at the top (e.g. interconnect 10 of FIG. 1a), the interconnect requires more space than it would if it had vertical sidewall surfaces. The packing density of an integrated circuit is therefore sacrificed by the sloped sidewall surfaces of interconnects. The amount of interconnect routing across a single horizontal level of an integrated circuit could be increased by the development of interconnect having vertical sidewall surfaces or, at the very least, more controlled placement of sidewall surfaces relative to one another. Packing density limitations further limit operation speed and circuit complexity. It is therefore desirable that a semiconductor fabrication process be developed for the formation of interconnect which allows higher density layout of advanced ULSI integrated circuits.